The present invention relates to semiconductor integrated circuits and more particularly to synchronizing read data from a memory device with a memory controller""s clock signal.
Certain types of memory devices generate a clock strobe signal having edges that are aligned with changes in the read data. A double data rate (DDR) dynamic random access memory (DRAM) transfers data on each rising and falling edge of the clock strobe signal. A DDR DRAM therefore transfers two data words per clock cycle.
A memory controller is often used to coordinate the transfer of data to and from a memory device, such as a DDR DRAM. The memory controller provides a local clock signal to the memory device for synchronizing read and write operations. The clock strobe signal generated by the memory device with the read data has predefined phase constraints with respect to the local clock signal provided by the memory controller. The memory controller uses the clock strobe signal for determining when the read data is valid and can therefore be latched. The times at which the read data is latched are preferably synchronized relative to the clock strobe signal so as to latch the read data in the middle of the valid data window.
Due to varying propagation delays from the memory controller""s local clock signal and the clock strobe signal that is received from the memory device, the phase relationship between the captured read data and the local clock signal can change from one device to the next and can change over time. These changes in phase alignment can be caused by input/output (I/O) pad delay variations, power supply fluctuations, process variations, temperature variations and variations in the clock input to data clock strobe output characteristics of the memory device. In certain cases these changes can be large enough to cause the captured read data to cross a metastable region with respect to the memory controller""s clock.
Due to these and other factors, accurate synchronization of the captured read data to the memory controller""s clock requires the phase relationship between the data output clock strobe signal and the memory controller""s clock to be known. Currently, there is no known method or system for measuring and correcting for changes in this phase relationship. Improved memory controller circuits are therefore desired that are capable of measuring the phase relationship between a memory controller""s clock and captured read data from a memory device, where the data is aligned with respect to a delayed clock strobe signal that originates from the memory device.
One embodiment of the present invention is directed to a phase measurement circuit which includes first and second complementary clock strobe inputs, a local clock input and a sample clock output. A programmable delay line is coupled between the local clock input and the sample clock output and has a plurality of propagation delay settings. First and second toggle circuits are clocked by the first and second clock strobe inputs, respectively, and each has a toggle output that changes state when clocked by the respective first or second clock strobe input. A capture latch circuit has first and second data inputs coupled to the toggle outputs of the first and second toggle circuits, respectively, has first and second capture outputs, and is clocked by the sample clock output. A synchronizer circuit has first and second data inputs coupled to the first and second capture outputs, respectively, has first and second synchronized capture outputs, and is clocked by the local clock input.
Another embodiment of the present invention is directed to a method of measuring a phase difference between a sample clock signal and captured data read from a memory device. The data is aligned with respect to a clock strobe signal originating from the memory device, which has constraints with respect to a local clock signal supplied to the memory device. The method includes: (a) delaying the local clock signal with a programmable delay line to produce the sample clock signal, wherein the programmable delay line has a plurality of programmable delay settings; (b) toggling a first logic bit between a first logic state and a second, different logic state with each change of the clock strobe signal from the first logic state to the second logic state; (c) toggling a second logic bit between the first and second logic states with each change of an inverse of the clock strobe signal from the first logic state to the second logic state; (d) capturing the states of the first and second logic bits as a function of the sample clock signal to produce first and second captured logic states; (e) synchronizing the first and second captured logic states to the local clock signal to produce synchronized, first and second captured logic states; and (f) measuring the phase difference as a function of the synchronized, first and second captured logic states.
Yet another embodiment of the present invention is directed to an apparatus for measuring a phase difference between a sample clock signal and captured data read from a memory device. The data is aligned with respect to a clock strobe signal originating from the memory device, which has constraints with respect to a local clock signal supplied to the memory device. The apparatus includes a programmable delay line having a plurality of programmable delay settings for delaying the local clock signal to produce the sample clock signal. A first toggle circuit toggles a first logic bit between a first logic state and a second, different logic state with each change of the clock strobe signal from the first logic state to the second logic state. A second toggle circuit toggles a second logic bit between the first and second logic states with each change of an inverse of the clock strobe signal from the first logic state to the second logic state. A logic state capture circuit captures the states of the first and second logic bits as a function of the sample clock signal to produce first and second captured logic states. A synchronizing circuit synchronizes the first and second captured logic states to the local clock signal to produce synchronized, first and second captured logic states. A measurement circuit measures the phase difference as a function of the synchronized, first and second captured logic states.